1. Field of the Invention
The invention relates to a chip package technology, and more particularly to a chip package having a lead structure capable of reducing electrostatic damage.
2. Description of Related Art
A packaging process is needed after a manufacturing process of an integrated circuit to package a core circuit into a chip with only a lead exposed for connecting an external circuit.
A variety of package technologies are available nowadays. For example, chip on film (COF) package technology is the latest trend. A lead for COF is a film lead. A connection terminal of an integrated circuit is, for example, a bumping pad which is electrically connected to the external circuit via the film lead.
In FIG. 1, a top schematic view of a connection structure between a bumping pad and a film lead of the conventional COF package is illustrated. Referring to FIG. 1, a plurality of bumping pads 102 is configured on a package body 100 of a chip. Each connection terminal 102 connects outwardly via a film lead 104. For example, the connection terminals 102 denoted by A, B, C, D, E, and F are connected by the same piece of the film lead 104, which is, for example, generally a lead for supplying power.
In general designs, since electrostatic discharge (ESD) is taken into consideration, each connection terminal 102 needs to have an electrostatic discharge protection circuit underneath, and one film lead 104 is likely to correspond to a plurality of the connection terminals 102. That is, a plurality of electrostatic discharge protection circuits is required. As a result, the area of an integrated circuit is occupied by the electrostatic discharge protection circuits and can not be effectively used.